cy62148vn mobl ? 4 mbit (512k x 8) static ram cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document number : 001-55636 rev. *a revised april 6, 2010 features wide voltage range: 2.7v to 3.6v ultra low active power low standby power ttl-compatible inputs and outputs automatic power down when deselected cmos for optimum speed and power package available in a 32-pin tsop ii and a 32-pin soic package functional description the cy62148vn is a high perf ormance cmos static ram organized as 512k words by eight bits. this device features advanced circuit design to provide ultra-low active current. this is ideal for providing more battery life ? (mobl ? ) in portable applications such as cellular telephones. the device also has an automatic power down feature th at significantly reduces power consumption by 99 percent wh en addresses are not toggling. the device can be put into standby mode when deselected (ce high). writing to the device is accomplished by taking chip enable (ce ) and write enable (we ) inputs low. data on the eight i/o pins (i/o 0 through i/o 7 ) is then written into the location specified on the address pins (a 0 through a 18 ). reading from the device is accomplished by taking chip enable (ce ) and output enable (oe ) low while forcing write enable (we ) high. under these conditions, the contents of the memory location specified by the address pins appear on the i/o pins. the eight input/ output pins (i/o 0 through i/o 7 ) are placed in a high impedance state when th e device is deselected (ce high), the outputs are disabled (oe high), or during a write operation (ce low and we low). for best practice recommendations, refer to the cypress application note an1064, sram system guidelines . logic block diagram 17 15 a 1 a 2 a 3 a 4 a 5 a 6 a 7 a 8 column decoder row decoder sense amps data in drivers power down we oe i/o 0 i/o 1 i/o 2 i/o 3 512k x 8 array i/o 7 i/o 6 i/o 5 i/o 4 a 0 a 12 a 14 a 13 a a 11 ce a a 16 a 10 18 a a 9 [+] feedback [+] feedback
cy62148vn mobl ? document number : 001-55636 rev. *a page 2 of 10 pin configuration figure 1. 32-pin tsop ii/soic (top view) product portfolio product v cc range (v) speed (ns) power dissipation operating i cc , (ma) standby i sb2 , ( ? a) min typ [1] max typ [1] max typ [1] max CY62148VNLL 2.7 3.0 3.6 70 7 15 2 20 we 1 2 3 4 5 6 7 8 9 10 11 14 31 32 12 13 16 15 29 30 v cc a 3 a 2 a 1 a 17 a 16 oe a 6 a 14 ce i/o 2 i/o 0 i/o 1 a 12 a 7 21 22 19 20 i/o 7 27 28 25 26 17 18 23 24 v ss a 5 a 4 i/o 6 i/o 5 i/o 4 i/o 3 a 10 a 18 a 11 a 0 a 9 a 8 a 13 a 15 note 1. typical values are included for reference only and are no t guaranteed or tested. typical values are measured at v cc = v cc(typ.) , t a = 25c. [+] feedback [+] feedback
cy62148vn mobl ? document number : 001-55636 rev. *a page 3 of 10 maximum ratings exceeding the maximum ratings may impair the useful life of the device. user guidelines are not tested. storage temperature ................................. ?65c to +150c ambient temperature with power applied ........................ ...................... 55c to +125c supply voltage to ground potential................?0.5v to +4.6v dc voltage applied to outputs in high-z state [2] .................................... ?0.5v to v cc + 0.5v dc input voltage [2] ................................ ?0.5v to v cc + 0.5v output current into outputs (l ow)............................. 20 ma static discharge voltage.......................................... > 2001v (per mil-std-883, method 3015) latch up current.................................................... > 200 ma operating range range ambient temperature v cc industrial ?40c to +85c 2.7v to 3.6v electrical characteristics over the operating range parameter description test conditions cy62148vn-70 unit min. typ. [1] max. v oh output high voltage i oh = ?1.0 ma v cc = 2.7v 2.4 v v ol output low voltage i ol = 2.1 ma v cc = 2.7v 0.4 v v ih input high voltage v cc = 3.6v 2.2 v cc + 0.5v v v il input low voltage v cc = 2.7v ?0.5 0.8 v i ix input load current gnd < v i < v cc ?1 + 1 +1 ? a i oz output leakage current gnd < v o < v cc , output disabled ?1 +1 +1 ? a i cc v cc operating supply current i out = 0 ma, f = f max = 1/t rc cmos levels v cc = 3.6v 7 15 ma i out = 0 ma, f = 1 mhz cmos levels 1 2 ma i sb1 automatic ce power down current? cmos inputs ce > v cc ? 0.3v, v in > v cc ?? 0.3v or v in < 0.3v, f = f max 2 20 ? a i sb2 automatic ce power down current? cmos inputs ce > v cc ?? 0.3v v in > v cc ?? 0.3v or v in < 0.3v, f = 0 v cc = 3.6v capacitance tested initially and after any design or proce ss changes that may affect these parameters. parameter description test conditions max unit c in input capacitance t a = 25c, f = 1 mhz, v cc = 3.0v 6pf c out output capacitance 8 pf thermal resistance tested initially and after any design or proce ss changes that may affect these parameters. parameter description test conditions tsop ii soic unit ? ja thermal resistance (junction to ambient) still air, soldered on a 4.25 x 1.125 inch, four-layer printed circuit board tbd tbd ? c/w ? jc thermal resistance (junction to case) tbd tbd ? c/w note 2. v il(min.) = ?2.0v for pulse durations less than 20 ns. [+] feedback [+] feedback
cy62148vn mobl ? document number : 001-55636 rev. *a page 4 of 10 figure 2. ac test loads and waveforms parameters 3.0v unit r1 1105 ? r2 1550 ? r th 645 ? v th 1.75v v data retention characteristics over the operating range parameter description conditions min. typ. [1] max. unit v dr v cc for data retention 1.0 3.6 v i ccdr data retention current v cc = 1.0v, ce > v cc ?? 0.3v, v in > v cc ?? 0.3v or v in < 0.3v; no input may exceed v cc + 0.3v 0.2 5.5 ? a t cdr [3] chip deselect to data retention time 0 ns t r [4] operation recovery time t rc ns figure 3. data retention waveform v cc typ v cc output r2 50 pf including jig and scope gnd 90% 10% 90% 10% rise time: 1v/ns fall time: 1v/ns output v th equivalent to: th venin equivalent all input pulses r1 r th 1.0v 1.0v t cdr v dr > 1.0 v data retention mode t r ce v cc notes 3. tested initially and after any design or proce ss changes that may affect these parameters. 4. full-device ac operation requires linear v cc ramp from v dr to v cc(min.) > 10 ? s or stable at v cc(min.) > 10 ? s. [+] feedback [+] feedback
cy62148vn mobl ? document number : 001-55636 rev. *a page 5 of 10 switching characteristics over the operating range [5] parameter description 70 ns unit min max read cycle t rc read cycle time 70 ns t aa address to data valid 70 ns t oha data hold from address change 10 ns t ace ce low to data valid 70 ns t doe oe low to data valid 35 ns t lzoe oe low to low z [ 6 ] 5ns t hzoe oe high to high z [ 7 ] 25 ns t lzce ce low and to low z [ 6 ] 10 ns t hzce ce high to high z [ 6, 7 ] 25 ns t pu ce 1 low and ce 2 high to power up 0 ns t pd ce 1 high and ce 2 low to power down 70 ns write cycle [8, 9] t wc write cycle time 70 ns t sce ce 1 low and ce 2 high to write end 60 ns t aw address setup to write end 60 ns t ha address hold from write end 0 ns t sa address setup to write start 0 ns t pwe we pulse width 50 ns t sd data setup to write end 30 ns t hd data hold from write end 0 ns t hzwe we low to high z [ 6, 7 ] 25 ns t lzwe we high to low z [ 6 ] 10 ns notes 5. test conditions assume signal transition time of 5 ns or less, timing reference levels of 1.5v, input pulse levels of 0 to v cc(typ.) , and output loading of the specified i ol /i oh and 30 pf load capacitance. 6. at any given temperature and voltage condition, t hzce is less than t lzce , t hzoe is less than t lzoe , and t hzwe is less than t lzwe for any given device. 7. t hzoe , t hzce , and t hzwe are specified with c l = 5 pf as in (b) of ac test loads. transition is measured 200 mv from steady-state voltage. 8. the internal write time of the memory is defined by the overlap of ce low and we low. both signals must be low to initiate a write and either signal can terminate a write by going high. the data input set-up and hold timing should be referenced to the rising edge of the signal that termina tes the write. 9. the minimum write cycle time for write cycle #3 (we controlled, oe low) is the sum of t hzwe and t sd . [+] feedback [+] feedback
cy62148vn mobl ? document number : 001-55636 rev. *a page 6 of 10 switching waveforms figure 4. read cycle no. 1: address transition controlled [10, 11] figure 5. read cycle no. 2: oe controlled [11, 12] figure 6. write cycle no 1: we controlled [8, 13, 14] previous data valid data valid rc t aa t oha t rc address data out 50% 50% data valid t rc t ace t doe t lzoe t lzce t pu data out high impedance impedance i cc i sb t hzoe t hzce t pd oe ce high v cc supply current t hd t sd t pwe t sa t ha t aw t wc data i/o address ce we oe t hzoe data in valid note 15 notes 10. the device is continuously selected. oe , ce = v il . 11. we is high for read cycle. 12. address valid before or similar to ce transition low. 13. data i/o is high impedance if oe = v ih . 14. if ce goes high simultaneously with we = v ih , the output remains in a high impedance state. [+] feedback [+] feedback
cy62148vn mobl ? document number : 001-55636 rev. *a page 7 of 10 figure 7. write cycle 2: ce controlled [8, 13, 14] figure 8. write cycle 3: we controlled, oe low [14] switching waveforms (continued) t wc t aw t sa t ha t hd t sd t sce we data i/o address ce data in valid data i/o address t hd t sd t lzwe t sa t ha t aw t wc ce we t hzwe data in valid note 15 note 15. during this period, the i/os are in output state. do not apply input signals. [+] feedback [+] feedback
cy62148vn mobl ? document number : 001-55636 rev. *a page 8 of 10 typical dc and ac characteristics truth table ce we oe inputs/outputs mode power h x x high-z deselect/power down standby (i sb ) l h l data out read active (i cc ) l l x data in write active (i cc ) l h h high-z output disabled active (i cc ) ordering information speed (ns) ordering code package name package type operating range 70 CY62148VNLL-70zsxi 51-85095 32-pin tsop ii industrial 70 80 60 40 30 20 1.0 1.9 2.8 3.7 supply voltage (v) access time vs. supply voltage 10 50 t aa (ns) 40 45 35 25 20 15 1.0 1.9 2.8 3.7 10 30 i sb ( ? a) standby current vs. supply voltage supply voltage (v) 1.2 1.4 1.0 0.6 0.4 0.2 1.7 2.2 2.7 3.2 3.7 0.0 0.8 i cc normalized operating current supply voltage (v) vs. supply voltage [+] feedback [+] feedback
cy62148vn mobl ? document number : 001-55636 rev. *a page 9 of 10 package diagrams figure 9. 32-pin tsop ii, 51-85095 51-85095 *a [+] feedback [+] feedback
document number : 001-55636 rev. *a revised april 6, 2010 page 10 of 10 mobl is a registered trademark and more battery life is a trademark of cypress semiconductor. all product and company names men tioned in this document are the trademarks of their respective holders. cy62148vn mobl ? ? cypress semiconductor corporation, 2009-2010. the information contained herein is subject to change without notice. cypress s emiconductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or ot her rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreemen t with cypress. furthermore, cypress does not authorize its products for use as critical components in life-support syst ems where a malfunction or failure may reas onably be expected to result in significa nt injury to the user. the inclusion of cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. any source code (software and/or firmware) is owned by cypress semiconductor corporation (cypress) and is protected by and subj ect to worldwide patent protection (united states and foreign), united states copyright laws and international treaty provisions. cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the cypress source code and derivative works for the sole purpose of creating custom software and or firmware in su pport of licensee product to be used only in conjunction with a cypress integrated circuit as specified in the applicable agreement. any reproduction, modification, translation, compilation, or repre sentation of this source code except as specified above is prohibited without the express written permission of cypress. disclaimer: cypress makes no warranty of any kind, express or impl ied, with regard to this material, including, but not limited to, the implied warranties of merchantability and fitness for a particular purpose. cypress re serves the right to make changes without further notice to t he materials described herein. cypress does not assume any liability arising out of the application or use of any product or circuit described herein. cypress does not authori ze its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress? prod uct in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. use may be limited by and subject to the applicable cypress software license agreement. document history page sales, solutions, and legal information worldwide sales and design support cypress maintains a worldwide network of offices, solution center s, manufacturer?s representative s, and distributors. to find t he office closest to you, visit us at cypress.com/sales. products psoc psoc.cypress.com clocks & buffers clocks.cypress.com wireless wireless.cypress.com memories memory.cypress.com image sensors image.cypress.com document title: cy62148vn mobl ? , 4 mbit (512k x 8) static ram document number: 001-55636 rev. ecn no. orig. of change submission date description of change ** 2761558 vkn 09/09/2009 new data sheet *a 2905443 vkn 06/04/2010 removed inactive part CY62148VNLL-70sxi from ordering information. updated package diagrams. [+] feedback [+] feedback
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